Summary

Graduate student in Computer Engineering at Texas A&M with 3+ years at ISRO in DSP-focused RTL design and fixed-point arithmetic optimization. Seeking a Summer/Fall 2026 internship in system and firmware engineering.

Education

Technical Skills

• HDLs & Design: Verilog HDL, SystemVerilog, UVM
• EDA & Simulation Tools: Cadence Xcelium, Cadence Innovus, Cadence Design Vision, Xilinx Vivado, Cadence Spectre, Synopsys VCS, Synopsys Primetime
• DSP & Signal Processing: FIR filter design, decimation, fixed-point arithmetic, I/Q generation, matched filtering
• Programming & Scripting: MATLAB, Python, C, C++, Make, Linux
• Physical Design: Synthesis (Design Vision), Place & Route (Innovus), static timing analysis, parasitic extraction
• Core Competencies: RTL design, DSP algorithm development, MATLAB modeling, functional verification, test vector generation

Professional Experience

• Developed synthesizable Verilog RTL for a multi-channel DSP pipeline on Xilinx Kintex-7 FPGA, implementing CORDIC-based DDC, FIR decimation filters, matched filtering with peak detection, and I/Q generation across three 153 MSPS / 16-bit ADC parallel data paths.
• Designed a multithreaded real-time C application processing FPGA-streamed radar data over Ethernet for Kalman filter-based range estimation, operator control, and real-time display.
• Implemented FIR decimation filters supporting multiple pulse widths (1 µs, 0.5 µs) using statically configured coefficients.
• Developed a MATLAB golden model of the full DSP chain to validate algorithm correctness prior to RTL implementation.
• Implemented fixed-point arithmetic and word-length optimization across the RTL pipeline, achieving ~90 dB dynamic range and -110 dBm sensitivity while minimizing FPGA resource usage.
• Interfaced design pipeline with three simultaneous 16-bit ADC channels at 153 MSPS, meeting a 3.4 ms real-time processing constraint.
• Debugged RTL data path using simulation and on-chip ILA instrumentation to identify channel skew, fixed-point scaling errors, and inter-channel misalignment.
• Performed RF bench characterization using spectrum analyzer, signal generator, and VNA to verify system sensitivity, noise figure, dynamic range, and inter-channel gain/phase matching.
• Documented design specs, timing constraints, and fixed-point scaling decisions to support design reviews.

Projects

• Architected a UVM-based coverage-driven verification environment for a 32-bit RISC-V (RV32IMZicsr) CPU with monitors, scoreboards, functional coverage models, and automated regression infrastructure.
• Verified ISA compliance via co-simulation against a C++ golden reference model; debugged mismatches in ALU, branch, CSR, and interrupt pathways using waveform analysis and assertion-based checks.
• Achieved 97% functional coverage across instruction categories; developed Python-based regression scripts to track coverage convergence and flag regressions.

• Developed a UVM testbench for YAPP protocol verification, integrating HBUS, Clock/Reset, and multichannel UVCs into a single environment.
• Created constrained-random and directed sequences to generate valid and corner-case scenarios for multiple YAPP channels; connected scoreboard using TLM analysis ports with reference model to detect dropped or corrupted packets.
• Configured and synchronized multichannel sequencing to ensure correct interaction between YAPP and HBUS protocols during verification.

• Developed UVM-based verification environment with driver, monitor, scoreboard, and coverage components.
• Designed assertions and functional coverage models to validate protocol correctness.
• Built Python scripts to automate regression testing achieving 100% functional and 94.7% code coverage; debugged transaction and protocol-level issues using waveform analysis tools.

• Designed a pipelined RTL datapath for a RISC-V single-core processor in Verilog, implementing fetch, decode, issue, execute, and writeback stages with full hazard handling.
• Developed Verilog testbench to validate register updates, commit logic, and forwarding paths; debugged commit logic to ensure precise in-order retirement with correct program state.

• Implementing a mutation-based hardware fuzzer targeting the CVA6 RISC-V core; generating coverage-guided stimuli to trigger privilege escalation vulnerabilities and detect hardware security bugs.

• Implemented a TAGE branch predictor in ZSim featuring multiple prediction tables with multiple global histories.
• Integrated LLBP overriding, improving prediction accuracy in 7.2% of branches at 87.8% correctness, achieving up to 4x misprediction reduction on SPEC CPU benchmarks.
• Automated ZSim output parsing, misprediction rate aggregation, and cross-benchmark comparison across 13 benchmarks using Python scripts.